1. Field of the Invention
The present invention pertains to switching of cells or packets through a switching device such as a node of a telecommunications network, and particularly to the switching of cells/packets having different classes of priorities or quality of service.
2. Related Art and Other Considerations
It is common in telecommunications and other fields to route cells or packets, such as (for example) ATM (Asynchronous Transfer Mode) cells, between nodes of a network. To accomplish the routing, one or more of the nodes through which the cells travel may include a switching device. Typically such a switching device includes a switch core which has plural switch core ports. In some switch core configurations, the switch core is formed as a buffer matrix with a crosspoint occurring at each row/column intersection of buffers. In such configuration, generally a switch core port writes cells to buffers in an associated row of the buffer matrix, and reads out cells from an associated column of the buffer matrix. Often a switch core interface board or the like interconnects a switch core port with network lines external to the node.
Various aspects of an example switch core for ATM-based telecommunications are explained in the following: U.S. patent application Ser. No. 09/188,101 [PCT/SE98/02325] and Ser. No. 09/188,265 [PCT/SE98/02326] entitled “Asynchronous Transfer Mode Switch”; U.S. patent application Ser. No. 09/188,102 [PCT/SE98/02249] entitled “Asynchronous Transfer Mode System”, all of which are incorporated herein by reference.
Cell switching nodes commonly handle cells of differing priority classes, e.g., cells having differing quality of service (QoS) designations. In a telecommunications context, for example, the cells belonging to very delay sensitive connections are labeled as being of a high priority, while cells belonging to less delay sensitive connections are labeled as being of a lower priority. The cell switching nodes usually handle high priority and low priority cells essentially concurrently.
To facilitate such concurrent handling of cells of differing priority, conventionally each crosspoint of the switch core's buffer matrix plural buffers has plural buffers (e.g., plural memory elements), usually one for each possible priority class or quality of service class. Incoming cells to the node are, upon receipt, typically queued in the switch core interface board, usually in a queue associated with the priority class of the cell. For example, incoming high priority cells are queued in a high priority queue of the switch core interface board, while incoming low priority cells are queued in a low priority queue of the switch core interface board. When it is determined to which crosspoint of the buffer matrix a queued high priority cell is to be written, the high priority cells is written into the buffer of the crosspoint that is allocated for high priority cells. Queued lower priority cells for the same crosspoint, on the other hand, are written to another buffer(s) of the crosspoint. Thus, the switch core is, in a sense, three dimensional, with a first dimension comprising rows of the matrix; a second dimension comprising columns of the matrix; and a third dimension comprising the various plural buffer memories for each of the corresponding plural priority classes.
Thus, in some conventional switch cores implemented in hardware, each priority class (e.g., quality of service (QoS) class) uses separate buffers. The plural buffers at each crosspoint feed the same switch core port for cell readout purposes, with the order of read out being based on the priority class of the buffers.
The number of buffers required for the switch core described above is thus the square of the number of switch core ports, multiplied by the number of priority classes handled by the switch core. This results in large memory requirements. When the switch core is fabricated using semiconductor memory, the large memory requirements involve a large silicon area.
What is needed therefore, and an object of the present invention, is a semiconductor switch core that economically handles cells of plural priority classes.